1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a dynamic semiconductor memory device storing information in the form of electric charges. More particularly, the invention relates to a structure in a dynamic semiconductor memory device for improving charge retention characteristics of memory cells. More specifically, the invention relates to a structure of circuitry for selecting word lines.
2. Description of the Background Art
FIG. 63 schematically shows a whole structure of a dynamic semiconductor memory device (will be referred to as "DRAM") in the prior art. In FIG. 63, the DRAM includes a memory cell array 900 having memory cells MC arranged in a matrix of rows and columns. In memory cell array 900, a word line WL is provided corresponding to each row of memory cells MC, and a column line (bit line pair BL and /BL) is provided corresponding to each column of memory cells MC. FIG. 63 representatively shows one word line WL and one bit line pair BL and /BL. Memory cell MC is provided corresponding to a crossing of bit line pair BL and /BL and word line WL. In FIG. 63, memory cell MC is provided corresponding to the crossing of bit line BL and word line WL, as an example. Memory cell MC includes a capacitor MQ storing information in the form of electric charges, and a memory transistor MT which is responsive to a signal potential on word line WL to be turned on to connect memory capacitor MQ to bit line BL (or /BL).
The DRAM further includes an address buffer 902 which produces an internal address signal from an externally applied address signal, a row decode circuit 904 which decodes the internal row address signal sent from address buffer 902 to produce a decode signal specifying a corresponding word line in memory cell array 900, and a word line drive circuit 906 which transmits a signal voltage indicative of the selected state onto the corresponding word line in accordance with the row decode signal from row decode circuit 904. Word line drive circuit 906, of which specific structure will be described later, transmits a high voltage Vpp higher than an operation power supply potential Vcc onto the selected word line (i.e., word line corresponding to the row specified by the address signal).
The DRAM further includes a sense amplifier group or band 908 including a plurality of sense amplifiers which are provided corresponding to respective bit line pairs BL and /BL, and differentially amplify signal potentials on the corresponding bit line pairs, a column decoder 910 which decodes the internal column address signal from address buffer 902 to produce a column select signal specifying a corresponding column (bit line pair) in memory cell array 900, an I/O gate circuit 912 which operates in accordance with the column select signal from column decoder 910 to connect the corresponding column (bit line pair) in the memory cell array to an internal data line (internal I/O line) 913, and an I/O circuit 914 for inputting and outputting external data DQ.
I/O gate circuit 912 includes column select gates provided corresponding to the respective bit line pairs. Upon writing of data, I/O circuit 914 produces internal write data from externally applied data DQ, and transmits the same to internal data line 913. Upon reading of data, I/O circuit 914 produces external read data DQ from internal read data on internal data line 913. In FIG. 63, I/O circuit 914 is shown to perform input and output of data through the same pin terminal. However, I/O circuit 914 may be adapted to perform input and output of data through different pin terminals.
For determining a timing of internal operation of the DRAM, there is provided a control signal generating circuit 916. Control signal generating circuit 916 receives a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and an output enable signal /OE, and generates various internal control signals. In FIG. 63, control signal generating circuit 916 is shown to apply internal control signals to address buffer 902 and row decoder 904.
When the row address strobe signal /RAS is activated, it attains the L-level and designates start of the memory cycle (start of access to the DRAM), and enables latching and decoding of the address signal, respectively, by address buffer 902 and row decode circuit 904. Address buffer 902 latches the address signal and produces the internal row address signal to apply the same to row decode circuit 904 when row address strobe signal /RAS attains the L-level. Row address strobe signal /RAS controls the operation of circuitry related to selection of a row in memory cell array 900.
Column address strobe signal /CAS determines the timing of operations related to column selection. When signal /CAS attains the L-level, address buffer 902 latches the externally applied address signal and produces the internal column address signal to apply the same to column decoder 910. Column decoder 910 decodes the applied address signal in accordance with the L-level of signal /CAS.
When activated, write enable signal /WE attains the L-level and indicates that the data write operation is designated. When activated, output enable signal /OE attains the L-level and designates that data of a selected memory cell is to be read out. Now, selecting operation of a memory cell of one bit will be briefly described below.
In response to the fall of signal /RAS, address buffer 902 takes in the externally applied address signal to produce the internal row address signal under the control by control signal generating circuit 916. Row decoder 904 decodes the internal row address signal thus produced under the control by control signal generating circuit 916, and produces a word line designating signal designating a word line WL. Word line drive circuit 906 raises the potential of the addressed word line WL in accordance with the word line designating signal from row decode circuit 904. As will be detailed later, word line drive circuit 906 raises the potential of the selected word line to high voltage Vpp higher than operation power supply voltage Vcc. The reason of boosting the potential of a selected word line will also be detailed later.
Memory transistor MT contained in memory cell MC connected to the selected word line is turned on to connect memory cell capacitor MQ to bit line BL (or /BL). The potential of bit line BL (/BL), which is kept in an electrically floating state at the intermediate potential Vcc/2 changes in accordance with information (accumulated electric charges) stored in memory capacitor MQ.
The sense amplifier contained in sense amplifier band 908 is activated under the control by control signal generating circuit 916, to amplify and latch the potential difference of each bit line pair BL and /BL.
When signal /CAS attains the L-level, address buffer 902 latches the externally applied address signal and produces the internal column address signal to apply the same to column decoder 910. Column decoder 910 is activated under the control by control signal generating circuit 916 to decode the internal column address signal from address buffer 902 and generate the column select signal specifying a corresponding column (bit line pair) in memory cell array 900.
I/O gate circuit 912 selects the corresponding column (bit line pair) in accordance with the column select signal from column decoder 910, and connects the selected column (bit line pair) to internal data line 913.
Writing and reading of data are performed depending on signals /WE and /OE. In the data writing operation, signal /WE attains the L-level, and I/O circuit 914 produces internal write data from externally applied write data D and transmits the internal write data onto the selected column via internal data line 913 and I/O gate circuit 912. In the data reading operation, signal /OE attains the L-level, and I/O circuit 914 produces and outputs external read data Q from the internal read data on internal data line 913.
FIG. 64 shows an example of the structures of row decode circuit and word line drive circuit. In FIG. 64, there is shown the structures of portions related only to one word line WL.
In FIG. 64, row decode circuit 904 includes a row decoder 924 provided corresponding to the word line WL. Row decoder 924 includes an AND decoder 924a receiving a predetermined combination of internal row address signals from the address buffer, and an inverter 924b inverting an output WD of AND decoder 924a. Both outputs of AND decoder 924a and inverter 924b have a swing of Vcc (i.e., its H-level is equal to power supply voltage Vcc, and its L-level is equal to the ground potential level). AND decoder 924a is set to the selected state and outputs the signal at H-level, when all the applied address signals are at the H-level.
Word line drive circuit 906 includes a word line driver 926 provided corresponding to each word line WL. Word line driver 926 includes an n-channel MOS transistor N1 transmitting a decoded signal WD sent from a corresponding row decoder 924, an n-channel MOS N2 which is turned on to transmit a boosted word line drive signal RX onto word line WL in response to the signal potential on node A, and an n-channel MOS transistor N3 which is turned on to discharge word line WL to the ground potential level in response to an inverted decoded signal ZWD sent from the corresponding row decoder 924.
An RX generating circuit 930 is activated in response to the fall of signal /RAS, and outputs the high voltage Vpp generated by a high voltage generating circuit 932 as word line drive signal RX at a predetermined timing. Operation will now be described below.
During standby state, row decoder 924 is kept at the precharged state under the control by control signal generating circuit 916 shown in FIG. 63, output WD of AND decoder 924a is at the L-level, and signal ZWD supplied from inverter 924b is at the H-level. In this state, MOS transistor N2 is off, and MOS transistor N3 is on. Word line WL has been discharged to the ground potential level via MOS transistor N3.
When signal /RAS attains the L-level, the memory cycle starts. Row decoder 924 is activated in accordance with the external control signal sent from control signal generating circuit 916 shown in FIG. 63, and decodes the address signal applied from the address buffer 902. When signal WD sent from row decoder 924 is at the H-level, node A is charged to the potential level of (Vcc-Vth) which is lower than power supply potential Vcc by the threshold voltage Vth of MOS transistor N1. Signal ZWD is at the L-level, and MOS transistor N3 is off.
After node A is charged, the potential of the boosted signal RX generated by RX generating circuit 930 rises and is applied to one conduction terminal (drain) of MOS transistor N2. In MOS transistor N2, owing to the capacitive coupling between the gate and the drain, the potential of node A rises (self-boosting operation), and the gate potential of MOS transistor N2 rises. Thereby, word line WL receives the boosted signal RX via the MOS transistor, and the potential of word line WL is raised to high voltage Vpp level higher than power supply potential Vcc. When the signal WD sent from row decoder 924 is at the L-level, the potential of node A does not rise and MOS transistor N2 maintains the off state, even if word line drive signal RX sent from RX generating circuit 930 rises. At this time, signal ZWD is at the H-level, MOS transistor N3 is on, and the potential of word line WL is at the ground potential level.
By the following reason, the potential of node A maintains the L-level when the signal of node A is at the L-level, even if the signal RX rises. When node A is charged to the potential level of (Vcc-Vth) (i.e., when signal WD is at the H-level of Vcc level), MOS transistor N1 is substantially off (i.e., has a potential difference of threshold voltage Vth between gate and source). When the signal RX rises, MOS transistor N1 becomes completely turned off when the potential of node A rises owing to the capacitive coupling, and the charges in node A are confined. Thus, node A is set to the electrically floating state, so that the potential thereof is raised to a value not lower than (Vcc+Vth). Meanwhile, when signal WD is at the L-level, node A is also at the L-level, and MOS transistor N1 is on. Therefore, node A does not attain the floating state even when signal RX rises, and thus the potential of node A does not rise but maintains the L-level. Thus, MOS transistor N1 has a function as a decoupling transistor decoupling the node A from the output of row decoder 924 (output of AND decoder 924a) in response to the rise of the potential of node A.
The reason for raising word line drive signal RX to a level not lower than the operation power supply potential Vcc level is as follows. The potential of the selected word line can be raised to high voltage Vpp at a speed higher than that at which it is raised up to power supply potential Vcc. Therefore, stored information of the memory cell (accumulated charges of the memory capacitor) can be read onto the bit line (BL or /BL) at an earlier timing. A quantity Q of accumulated charges of the memory capacitor can be represented as Q=.multidot.Ce(V-Vcp), where V represents a potential of one electrode of the memory capacitor (i.e., storage node connected to the memory transistor), Vcp represents a potential of the other electrode (cell plate) of the memory capacitor, and C represents a capacitance of the memory capacitor. Therefore, in order to increase the quantity Q of accumulated charges of the memory capacitor, it is preferable to increase the potential V of the one electrode of memory capacitor as high as possible. One electrode of memory capacitor is connected to bit line (BL or /BL) via memory transistor MT as shown in FIG. 63. By setting the potential of word line WL to high voltage Vpp, the voltage at power supply potential Vcc level of bit line (BL or /BL) can be transmitted to the one electrode of memory capacitor MQ without loss of the threshold voltage of memory transistor MT. Thereby, an intended quantity of the accumulated charges is ensuredly accumulated in memory capacitor MQ.
In general, potential Vcp of the cell plate is set to an intermediate potential of Vcc/2. The potential transmitted to the one electrode of the memory capacitor is equal to power supply potential Vcc level when it is at the H-level, and is equal to the ground potential level when it is at the L-level. The reference potential (precharge potential) of bit lines BL and /BL is the intermediate potential Vcc/2. By transmitting the potential at power supply potential Vcc level as the high level of memory capacitor, the quantity of variation of the potential of bit line (BL or /BL) can be constant when reading data at the H-level and at the L-level from the memory capacitor, and thus the stable sense operation (i.e., increase of the sense margin and others) can be achieved.
FIG. 65 shows another structure of the word line select circuit in the prior art. In the structure shown in FIG. 65, the word driver itself has a decoding function.
In FIG. 65, row decoder 904 includes a row predecoder 940 which predecodes the internal address signal sent from the address buffer to generate a row predecode signal AX, an RX decoder 946 which predecodes a particular internal address signal sent from the address buffer to generate word line drive signals RXa (RX0-RX3 in FIG. 65), and a row decoder 942 which decodes the predecode signal sent from row predecoder 940 to generate signals WD and ZWD specifying the word line group including a plurality of word lines.
Row predecoder 940 generates the predecode signals (which are representatively indicated by AX0, AX1 and AX2 in FIG. 65) for specifying the word line group including a predetermined number of (four in FIG. 65) word lines. Row decoder 942 is provided corresponding to the word line group, and generates the decode signal for simultaneously designating the word lines included in the corresponding word line group. Row decoder 942 includes an AND decoder 943 receiving the predecode signal supplied from row predecoder 940, and an inverter 945 inverting the output of AND decoder 943. AND decoder 943 and inverter 945 use high voltage Vpp as the operation power supply potential, and operate to decode the predecode signal applied from row predecoder 940 and having a swing of power supply potential Vcc level and convert the potential of the decoded signal at the high level into high voltage Vpp level. The signal at the ground potential level is not converted, and is output as the signal at the ground potential level.
RX decoder 946 includes an X-predecoder 947 which predecodes the internal address signal sent from the address buffer, and a level converter circuit 949 which converts the H-level of the output of X-predecoder 947 into high voltage Vpp level for generating word line drive signals RX0-RX3. One of word line drive signals RX0-RX3 sent from the level converter circuit 949 is set to the H-level, and the remaining three word line drive signals are set to the L-level (ground potential level).
In word line drive circuit 906, a plurality of (four in FIG. 65) word drivers 950a-950d are provided for one row decoder 942. Word drivers 950a-950d receive word line drive signals RX0-RX3 from RX decoder 946, respectively. Word drivers 950a-950d have the same structure and, more specifically, each includes an n-channel MOS transistor N4 which transmits decode signal WD sent from row decoder 942 to an internal node B, an n-channel MOS transistor N5 which transmits word line drive signal RXi (i=0-3) to corresponding word line WLi in response to the signal potential on node B, and an n-channel MOS transistor N6 which discharges word line WLi to the ground potential in response to decode signal ZWD sent from row decoder 942. MOS transistor N4 is supplied at its gate with high voltage Vpp. Operation will now be described below.
Signals WD and ZWD output from row decoder 942 are at the L- and H-levels, respectively, when the decoder 942 is in the standby state or nonselected state (i.e., when at least one of outputs AX0, AX1 and AX2 of row predecoder 940 is at the L-level). In this state, the potential of node B is at the L-level, MOS transistor N5 is off, and MOS transistor N6 is on, so that all word lines WL0-WL3 are held at the ground potential level.
In the operation, when all outputs AX0, AX1 and AX2 of row predecoder 940 are at the H-level, outputs WD and ZWD of row decoder 942 are at the H- and L-levels, respectively. MOS transistor N6 is off, and MOS transistor N5 is on. The potential of node B is at the level of (Vpp-Vth), where Vth is the threshold voltage of MOS transistor N4. Signal WD is at the high voltage Vpp level. MOS transistor N4 is substantially off. In this state, one of word line drive signals RX0-RX3 supplied from RX decoder 946 rises to the H-level of high voltage Vpp level.
It is now assumed that word line drive signal RX0 is at the high voltage Vpp level, and other word line drive signals RX1-RX3 are at the L-level of the ground potential level. In the word driver 950a, the potential of node B rises to the potential level not lower than (Vpp+Vth) owing to the self-boost effect of MOS transistor N5, where Vth is the threshold voltage of MOS transistor N5. Thereby, MOS transistor N5 transmits word line drive signal RX0 at high voltage Vpp level onto word line WLO without the loss of the threshold voltage. In word drivers 950b-950d, word line drive signals RX1-RX3 are at the L-level of the ground potential level, and the signals at the L-level of the ground potential level are transmitted onto word lines WL1-WL3 via MOS transistors N5, respectively.
FIG. 66 shows still another structure of the conventional word line driver circuit. FIG. 66 shows a structure of the word driver provided for one word line. In FIG. 66, the word driver includes a p-channel MOS transistor P1 which raises word line WL to high voltage Vpp level in response to decode signal ZWD, and n-channel MOS transistor N1 which discharges word line WL to the ground potential level in response to decode signal ZWD. The H-level of decode signal ZWD which is supplied from a decode stage (not shown) is equal to high voltage Vpp level, and the L-level thereof is equal to the ground potential level. Decode signal ZWD designates only one word line. p-channel MOS transistor P1 receives high voltage Vpp at one conduction terminal (source), and is connected at the other conduction terminal (drain) to word line WL. The n-channel MOS transistor N1 has one conduction terminal (source) connected to receive the ground potential, connected to a gate receive decode signal ZWD, and the other conduction terminal (drain) connected to word line WL. The word driver shown in FIG. 66 has a structure of a CMOS inverter circuit which operates with high voltage Vpp and ground potential. Operation will now be described below. In the standby state or nonselected state, signal ZWD is at high voltage Vpp level. MOS transistor P1 is off, and MOS transistor N1 is on, so that word line WL is discharged to the ground potential level. When signal ZWD attains the L-level of the ground potential level, MOS transistor N1 is turned off, and MOS transistor P1 is turned on, so that high voltage Vpp is transmitted to word line WL.
FIG. 67 shows a specific structure of the memory cell array. In FIG. 67, there are shown memory cells MC00, MC01, MC10 and MC11 arranged in two rows and two columns. Memory cells MC00 and MC10 are connected to word line WL0, and memory cells MC01 and MC11 are connected to word line WL1. Memory cells MC00 and MC01 are connected to bit line pair BL and /BL, and memory cells MC10 and MC11 are connected to bit line pair BL1 and /BL1.
A precharge/equalize circuit PEO and a sense amplifier SAO are provided for bit line pair BL0 and /BL0, and precharge/equalize circuit PE1 and sense amplifier SA1 are provided for bit line pair BL1 and /BL1.
Each of precharge/equalize circuits PE0 and PE1 includes n-channel MOS transistors T2 and T3, which are turned on in response to a bit line equalize signal BEQ to transmit a predetermined intermediate potential VBL to corresponding bit lines IBL and BL, and an n-channel MOS transistor T1, which is turned on in response to equalize signal BEQ to electrically short-circuit the bit lines BL0 (BL1) and /BL0 (/BL1). Generally, there is a relationship of VBL=Vcp=Vcc/2.
Bit line equalize signal BEQ is activated to precharge and equalize the bit lines BL0 (BL1) and /BL0 (/BL1) to intermediate potential VBL (=Vcc/2) when the signal /RAS is "H" of inactive state. When the signal /RAS attains the active state of the L-level, the bit line equalize signal BEQ attains the inactive state of the L-level, so that transistors T1, T2 and T3 are turned off, and bit lines BL0 (BL1) and /BL0 (/BL1) are set to the electrically floating state at the intermediate potential. When word line (e.g., WL0) is selected and its potential rises, memory transistors MT in memory cells MC00 and MC10 are turned on, and potentials of bit lines BL0 and BL1 change from precharge potential VBL in accordance with information stored in memory cells MC00 and MC10. Bit lines /BL0 and /BL1 hold the precharge potential. Thereafter, sense amplifiers SA0 and SA1 are activated to amplify potential differences of bit lines BL0 and /BL0, and bit lines BL1 and /BL1, respectively. In the DRAM, memory capacitor MQ stores information in the form of electric charges. Leak of charges from the capacitor reduces the amount of accumulated charges. The leak of accumulated charges from the memory capacitor will be discussed below.
As shown in FIG. 68, it is assumed that data at the H-level (i.e., signal at power supply potential Vcc level) is written into memory cell MC. Upon completion of data writing, word line WL attains the nonselected state of the ground potential level (0 V). During the standby state, bit line BL is kept at the potential of Vcc/2 set by the precharge/equalize circuit shown in FIG. 67. In memory capacitor MQ, the potential of a storage node SN is Vcc, and the potential of cell plate SP is Vcp. In this state, the potential of gate of memory transistor MT is sufficiently lower than the potential of its source (i.e., conduction terminal connected to bit line BL). Therefore, even if the potential of word line WL varies to some extent, e.g., due to the influence by noises, memory transistor MT surely maintains the off state, and hence the electric charges neither flow from memory capacitor MQ into bit line BL nor flow from bit line BL into memory capacitor MQ.
As shown in FIG. 69, it is now assumed that memory cell MC1 has stored data at the H-level, and memory transistor MT1 is connected to word line WL0. Memory cell MC2 is connected to word line WL1, and has stored data at the L-level. Memory transistors MT1 and MT2 are connected to bit line BL. When word line WL1 is selected to raise its potential, data held at memory cell MC2 is transmitted onto bit line BL. Thereafter, the sense amplifier operates and the potential of bit BL is discharged down to the ground potential (0 V). In this state, the gate and source of transistor MT1 in the memory cell MC1 are set to the same potential. In this state, therefore, memory cell MC1 has the electric charges held at memory capacitor MQ1 flown to bit line BL when the potential of word line WL0 rises due to the capacitive coupling with word line WL1, or when the potential of bit line BL slightly decreases in the negative direction due to the capacitive coupling between word line WL1 and bit line BL at the time of fall of the potential of word line WL1. In this manner, the potential change of the word line or bit line causes leak of charges accumulated in the memory capacitor via the channel of the memory transistor, and this leak causes change of the charge retention characteristics, which is referred to as "disturb refresh".
As shown in FIG. 70, it is assumed that memory capacitor MQ has stored data at the L-level during the standby state. The source of MOS transistor is one of the two conduction terminals held at the potential lower than that of the other. In the case shown in FIG. 70, therefore, the source is the conduction terminal connected to storage node SN. Even in this case, when the potential of word line WL rises due to the influence by noises, charges flow into memory capacitor MQ. This results in destruction of the stored information due to leak of electrons in the memory capacitor. Therefore, even the case shown in FIG. 70 presents a problem that sufficient immunity against "disturb refresh" cannot be achieved.
FIG. 71 shows an example of a subthreshold current characteristics of the MOS transistor. FIG. 71 shows a relationship between a gate/source voltage V.sub.GS and a drain current I.sub.D with a drain/source voltage V.sub.DS of 0.1 V. When gate voltage V.sub.GS is lower than the threshold voltage, drain current I.sub.D decreases exponentially. However, a small current flows even when the potentials of the gate and the source are equal to each other. If the electrostatic capacitance of memory cell capacitor MQ is relatively large, the leak does not significantly affect the refresh cycle. However, if the capacitance of memory capacitor is greatly reduced so as to comply with high integration of DRAM in recent years, the amount of accumulated charges decreases, so that the leak current significantly affects the refresh cycle.
In order to prevent the flow of charges which may be caused by the channel leak, the impurity concentration at the channel region may be increased sufficiently for increasing the threshold voltage Vth of memory transistor MT. The subthreshold current which may cause the channel leak is the drain current through a weakly inverted region in the channel region, and formation of this weakly inverted region is suppressed by increasing the threshold voltage.
However, if the threshold voltage Vth of memory transistor MT is raised as described above, it is necessary to further increase the voltage of high voltage Vpp applied to word line WL in order to write the signal potential at power supply potential Vcc level (i.e., H-level data) into memory capacitor MQ. If the high voltage Vpp is increased, a load of the circuit generating the high voltage Vpp increases, so that stable supply of high voltage Vpp is impossible, or the circuit scale or size must be increased. Also, current consumption increases by the following reason. In general, a high voltage generating circuit produces the high voltage Vpp from power supply potential Vcc by utilizing a charge pump operation of a capacitor. An efficiency of conversion from power supply potential Vcc to high voltage vpp is not higher than 50%. For example, if the current consumption of the circuit utilizing the high voltage Vpp increases by 1 mw and the conversion efficiency is 50%, the current consumption of power supply potential Vcc increases by 2 mW. Further, if high voltage Vpp is increased, a high voltage is applied to the word line, which results in a problem related to the reliability of breakdown voltage characteristics of the word line as well as a problem related to the reliability of the transistors supplied with high voltage Vpp (MOS transistor and memory transistor in the word driver). In particular, a problem related to reliability of components arises in the word driver portion, because high voltage Vpp is applied across the drain and source of the MOS transistor therein.
If the refresh cycle is shortened in order to compensate for deterioration of the refresh characteristics (charge retention characteristics of memory cell), only reading and rewriting (restoring) of data of memory cell are merely performed in the refresh operation, and external access is inhibited, so that an external device cannot access the DRAM during the refresh period, resulting in reduction of a utilization efficiency of the DRAM and in performance deterioration of a processing system using the DRAM.